The present invention relates to an improved method for plasma etching a multi-layer resist in the fabrication of semiconductor devices.
The performance of today's integrated circuit chips is related to the dimensions of the transistors and wiring interconnects in the integrated circuits. As the dimensions of the transistors and wiring interconnects continue to shrink, the ability to pattern smaller features using photolithography has been a primary factor driving the success of the integrated circuit industry.
Photolithography processes involve the use of lithography imaging tools and photoresist materials. The minimum resolution achievable with the lithography imaging is governed by the minimum resolution for an exposure wavelength and a resolving power or numerical aperture of a lens system used by the lithography imaging tool. A shorter exposure wavelength for a larger numerical aperture often results in high resolution in order to print smaller patterns in a resist film. However, decreasing the wavelength or increasing the numerical aperture often results in a decrease in the depth of focus (DOF), thereby requiring the reduction and the thickness of the photoresist film.
Simply reducing the thickness of the resist film to enhance resolution is effective up to a certain point. This point is reached when the resist becomes too thin to withstand subsequent etching processes that transfer the resist pattern to one or more layers under the resist film. In order to overcome these problems, bi-layer resists have been developed to extend the photolithography technology. A bilayer resist film typically includes a relatively thick lower resist layer (also referred to as a masking or planarizing layer) disposed over a wafer or substrate, and a relatively thin upper resist layer, or imaging layer, disposed on top of the lower resist layer. The upper resist layer is patterned by light exposure and subsequently developed. The resulting upper layer pattern is used as a mask for etching the lower resist layer. In this way, a resist pattern with high aspect ratio can be formed in the bilayer resist film.
In order to provide sufficient etch resistance to the upper resist layer when the bilayer resist undergoes a lower resist layer etching process, silicon is typically incorporated into the upper resist layer. Since the lower resist layer is typically made of organic polymers, an oxygen-based plasma is usually used to etch the lower resist layer, using the patterned top resist layer as a mask. Thus, while the lower resist layer is being etched in the oxygen based plasma, silicon precursors in the upper resist layer are oxidized to form a refractory oxide during the etching processes. The refractory oxide acts as an etch barrier, resulting in enhanced etching resistance of the upper resist layer. The enhancement achieved in this manner, however, is found in many applications to be insufficient.
The lower resist etching process not only requires good etch contrast between the upper resist layer and the lower resist layer, but also needs to be anisotropic to achieve good critical dimension (CD) control. With pure oxygen plasma, however, anisotropic etching can only be achieved when the temperature of the resist layers is maintained at or below about −100° C. during the etching process. Otherwise, lateral etching or undercutting is usually observed indicating CD loss. Multi-layer resists are available that include more than two layers and some of the problems mentioned above are prevalent.
In view of the foregoing, there is a need for a method and apparatus to provide alternative anisotropic etching conditions when etching a multi-layer resist.